Harvard type processor circuits are known in the prior art and are shown in FIG. 1. This Harvard architecture allows the processor circuit increased rapidity because instructions and data can be accessed at the same time. Processor circuits 1 having this architecture take the form of a calculation unit 2 communicating with two distinct memory units 3, 4. The first of the memory units 4 is used for storing instructions, while the second memory unit 3 is used for data storage. Each memory unit 3, 4 communicates with calculation unit 2 via a respective communication bus 5, 6. This architecture is thus characterized by the separation of data and instructions.
However, this type of architecture has some drawbacks. In fact, the architecture imposes two physically distinct memory units thereby increasing the surface area dedicated to said memory units and thus the surface area of the integrated processor circuit.
Moreover, this type of architecture with two separate memory units is not flexible to use. Indeed, even if it is possible to adapt the size of the two memory units in accordance with the use that will be made thereof, this adjustment requires physical alteration of the size of the two memory units. This alteration involves additional costs due to the need to perform design work on the actual component.
US Patent No 2002/0184465, which discloses a processor circuit using a similar architecture to the Harvard architecture, is also known in the prior art. This processor circuit is devised to have the processing speed advantages of the Harvard architecture. The processor circuit disclosed in US Patent No 2002/0184465 includes an architecture wherein the memory zone containing the instructions is also capable of storing data. However, this architecture still has two distinct memory units, one for instructions and one for data. The possibility of storing data in the memory unit that contains instructions allows some flexibility of use.
However, this processor circuit still has two distinct memory units with a large surface area which does not resolve the surface area problem of the Harvard architecture. Moreover, another drawback of this processor circuit is that it has flexibility of use resulting from a modification of the conventional Harvard architecture. Indeed, the processor circuit discloses a conventional Harvard architecture which still has two distinct memory units each communicating with the calculation unit via a communication bus. However, this architecture is altered in that the data bus is connected both to the data memory and to the programme memory. Thus, the flexibility provided by the processor circuit requires a profound alteration to the processor circuit and thus involves non negligible development costs.
Further, one of the drawbacks of storing data in the programme memory arises from the difference in size between data and instructions. It is generally observed that instructions are encoded in a larger number of bits than data. Thus, since the programme memory is divided into memory sections of the same size as that of the instructions, it may happen that several data items are stored in the same memory section. In read mode, the entire memory section is taken to be read. Thus when data stored in the instruction memory is read, only one part of the section is read which wastes time if successive data is read.